general description the max3690 serializer is ideal for converting 8-bit- wide, 77mbps parallel data to 622mbps serial data in atm and sdh/sonet applications. operating from a single +3.3v supply, this device accepts ttl clock and data inputs, and delivers a 3.3v differential pecl serial- data output. a fully integrated pll synthesizes an inter- nal 622mhz serial clock from a low-speed crystal reference clock (77.76mhz, 51.84mhz, or 38.88mhz). the max3690 is available in the extended-industrial temperature range (-40? to +85?) in a 32-pin tqfp package. ________________________applications 622mbps sdh/sonet transmission systems 622mbps atm/sonet access nodes add/drop multiplexers digital cross connects ____________________________features selectable reference clock frequency: 77.76mhz, 51.84mhz, or 38.88mhz single +3.3v supply 77mbps (8-bit) parallel to 622mbps serial conversion clock synthesis for 622mbps serial data 200mw power ttl parallel clock and data inputs differential 3.3v pecl serial-data output max3690 +3.3v, 622mbps, sdh/sonet 8:1 serializer with clock synthesis and ttl inputs ________________________________________________________________ maxim integrated products 1 max3690 max3668 sd- gnd pclko 38.88mhz ttl crystal reference pclki rclk v cc ckset sd+ fil- fil+ 130 ? 130 ? 82 ? 82 ? v cc = +3.3v v cc = +3.3v v cc = +3.3v overhead generation pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 this symbol represents a transmission line of characteristic impedance (z 0 = 50 ? ). 1 f 1 f typical operating circuit 19-4774; rev 2; 7/04 part MAX3690ECJ -40? to +85? temp range pin-package 32 tqfp ordering information pin configuration appears at end of data sheet. for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 1-800-835-8769. MAX3690ECJ+ -40? to +85? 32 tqfp + denotes lead-free package.
max3690 +3.3v, 622mbps, sdh/sonet 8:1 serializer with clock synthesis and ttl inputs 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3.0v to +3.6v, pecl loads = 50 ? ?% to (v cc - 2v), t a = -40 c to +85 c, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note 1: ac characteristics guaranteed by design and characterization. note 2: all ttl thresholds set to v cc / 2. terminal voltage (with respect to gnd) v cc .......................................................................-0.5v to +5v all inputs, fil-, fil+, pclko .................-0.5v to (v cc + 0.5v) output current pecl outputs (sd?.......................................................50ma continuous power dissipation (t a = +85?) tqfp (derate 10.2mw/? above +85?) .....................663mw operating temperature range ...........................-40? to +85? storage temperature range .............................-60? to +160? lead temperature (soldering, 10sec) .............................+300? t a = 0? to +85? pecl outputs unterminated i ol = -400? i oh = 400? v in = 0 v in = v cc t a = 0? to +85? conditions v cc - 1.025 v cc - 0.88 ma 60 100 i cc supply current v 0.44 v ol output low voltage v 2.4 v oh output high voltage ? -10 10 i il input low current ? -10 10 i ih input high current v cc - 1.81 v cc - 1.62 v 2.0 v ih input high voltage v 0.8 v il input low voltage units min typ max symbol parameter c load = 15pf, v out = 0.8v to 2.0v c load = 15pf, v out = 0.8v to 2.0v conditions ps 1000 t h parallel data hold time ps 1200 t su mhz 622.08 f sclk serial clock rate parallel data setup time ns 550 t f ttl output fall time ns 650 t r ttl output rise time ns 0 5.0 t skew allowable parallel clock output to parallel clock input delay ps rms 11 0 output random jitter units min typ max symbol parameter ac electrical characteristics (v cc = +3.0v to +3.6v, pecl loads = 50 ? ?% to (v cc - 2v), all ttl thresholds set to v cc /2, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?.) (note 1) ckset = 0 or v cc ? 500 i ckset ckset input current t a = -40? v v cc - 1.085 v cc - 0.88 v oh output high voltage t a = -40? v v cc - 1.83 v cc - 1.555 v ol output low voltage pecl outputs (sd) ttl inputs and outputs (pclki, rclk, pclko, pd_) 20% to 80% ps 200 t r, t f pecl differential output rise/fall time
max3690 +3.3v, 622mbps, sdh/sonet 8:1 serializer with clock synthesis and ttl inputs _______________________________________________________________________________________ 3 45 55 50 65 60 70 75 supply current vs. temperature max3690-01 temperature (?) supply current (ma) -50 25 -25 0 50 75 100 -95 -80 -85 -90 -70 -75 -60 -65 -55 parallel data setup time vs. temperature max3690-02 temperature ( c) parallel data setup time (ps) -40 25 -25 0507585 230 245 240 235 255 250 265 260 270 -40 25 -25 0 50 75 85 parallel data hold time vs. temperature max3690-03 temperature ( c) parallel data hold time (ps) -5 0 5 10 15 00 -50 50 100 allowed pclko to pclki skew vs. temperature max3690-07 temperature ( c) time (ns) 2mv/ div 5ps/div serial data random jitter (r clki = 77.76mhz) max3690-05 temperature ( c) v cc = 3.3v rj = 4.66ps rms __________________________________________typical operating characteristics (v cc = +3.3v, t a = +25?, unless otherwise noted.) 100mv/ div 200ps/div serial-data output eye diagram (622mbps, prbs) max3690-08
max3690 +3.3v, 622mbps, sdh/sonet 8:1 serializer with clock synthesis and ttl inputs 4 _______________________________________________________________________________________ ______________________________________________________________pin description name function 1? pd0?d7 ttl parallel-data inputs. data is clocked in on the pclki signal? positive transition. 9, 10, 17, 18, 19, 24, 25, 26, 31, 32 gnd ground pin 11 pclko ttl parallel-clock output. use positive transition of pclko to clock the overhead management circuit. 12, 13, 16, 21, 28, 29 v cc +3.3v supply voltage 20 ckset reference clock rate programming pin. ckset = open: reference clock rate = 77.76mhz ckset = 20k ? to gnd: reference clock rate = 51.84mhz ckset = gnd: reference clock rate = 38.88mhz 15 sd+ noninverting pecl serial-data output 14 sd- inverting pecl serial-data output 30 pclki ttl parallel-clock input. connect the incoming parallel-data-clock signal to the pclki input. the active edge is the positive transitioning edge. 27 rclk ttl reference-clock input. connect a crystal reference clock (77.76mhz, 51.84mhz or 38.88mhz) to the rclk input. the active edge is the positive transitioning edge. 23 fil+ filter capacitor input. connect a 1? capacitor between fil- and v cc . _______________detailed description the max3690 serializer comprises an 8-bit parallel input register, an 8-bit shift register, control and timing logic, a pecl output buffer, ttl input/output buffers, and a frequency-synthesizing pll (consisting of a phase/frequency detector, loop filter/amplifier, voltage- controlled oscillator, and programmable prescaler). this device converts 8-bit-wide, 77mbps parallel data to 622mbps serial data (figure 1). the pll synthesizes an internal 622mhz reference used to clock the output shift register. this clock is generated by locking onto the external crystal refer- ence clock signal (rclk) operating at either 77.76mhz, 51.84mhz, or 38.88mhz. the incoming par- allel data is clocked into the max3690 on the rising transition of the parallel-clock-input signal (pclki). the control and timing logic ensure proper operation if the parallel-input register is latched within a window of time that is defined with respect to the parallel-clock-output signal (pclko). pclko is the synthesized 622mhz internal serial-clock signal divided by eight. parallel- clock output to parallel-clock-input delay (skew) must be observed. figure 2 shows the timing diagram. pecl outputs the serial-data pecl outputs (sd+, sd-) require 50 ? dc termination to (v cc - 2v). see the alternative pecl- output termination section. 22 fil- filter capacitor input. connect a 1? capacitor between fil- and v cc .
max3690 +3.3v, 622mbps, sdh/sonet 8:1 serializer with clock synthesis and ttl inputs _______________________________________________________________________________________ 5 max3690 ttl pd7 ttl pd6 ttl 8-bit parallel input register phase/freq detect control 8-bit shift register pd5 ttl pd4 ttl pd3 ttl pd2 ttl pd1 ttl ttl pd0 ttl pclki ckset ttl fil+ fil- pclko vco rclk pecl sdoh sdol shift latch pre- scaler figure 1. functional diagram t su valid parallel data pclko pclki pd_ sd d7 d6 d5 d4 d3 d2 note: pd7 = d7, pd6 = d6, pd5 = d5, pd4 = d4, pd3 = d3, pd2 = d2, pd1 = d1, pd0 = d0 d1 d0 t h t skew figure 2. timing diagram
max3690 +3.3v, 622mbps, sdh/sonet 8:1 serializer with clock synthesis and ttl inputs 6 _______________________________________________________________________________________ __________applications information alternative pecl-output termination figure 3 shows alternative pecl-output-termination methods. use thevenin-equivalent termination when a (v cc - 2v) termination voltage is not available. if ac coupling is necessary, be sure that the coupling capacitor is placed following the 50 ? or thevenin- equivalent dc termination. layout techniques for best performance, use good high-frequency layout techniques. filter voltage supplies and keep ground connections short. use multiple vias where possible. also, use controlled-impedance transmission lines to interface with the max3690 data outputs. max3690 sd+ sd- v cc - 2v 50 ? 50 ? z 0 = 50 ? high- impedence inputs z 0 = 50 ? max3690 sd+ sd- +3.3v 130 ? 130 ? 82 ? 82 ? z 0 = 50 ? pecl inputs z 0 = 50 ? figure 3. alternative pecl-output termination
max3690 +3.3v, 622mbps, sdh/sonet 8:1 serializer with clock synthesis and ttl inputs _______________________________________________________________________________________ 7 tqfp top view fil+ fil- v cc ckset gnd gnd gnd gnd pd1 pd2 pd3 pd4 pd5 pd0 pd7 pd6 sd+ sd- gnd v cc v cc pclko v cc gnd gnd rclk gnd v cc v cc pclki gnd gnd 32 31 30 29 28 27 26 25 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 16 8 7 6 5 4 3 2 1 max3690 pin configuration
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. max3690 +3.3v, 622mbps, sdh/sonet 8:1 serializer with clock synthesis and ttl inputs tqfppo.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
|
